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HPCA
2011
IEEE
14 years 8 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISLPED
2005
ACM
122views Hardware» more  ISLPED 2005»
15 years 10 months ago
A simple mechanism to adapt leakage-control policies to temperature
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
Stefanos Kaxiras, Polychronis Xekalakis, Georgios ...
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
15 years 8 months ago
Transistor reordering rules for power reduction in CMOS gates
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
CORR
2010
Springer
100views Education» more  CORR 2010»
15 years 4 months ago
Radio Interface for High Data Rate Wireless Sensor Networks
This paper gives an overview of radio interfaces devoted for high data rate Wireless Sensor Networks. Four aerospace applications of WSN are presented to underline the importance ...
Julien Henaut, Aubin Lecointre, Daniela Dragomires...
FAST
2011
14 years 8 months ago
CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives
Although Flash Memory based Solid State Drive (SSD) exhibits high performance and low power consumption, a critical concern is its limited lifespan along with the associated relia...
Feng Chen, Tian Luo, Xiaodong Zhang