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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 27 days ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ECBS
1996
IEEE
155views Hardware» more  ECBS 1996»
13 years 11 months ago
Model-Integrated Program Synthesis Environment
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
Janos Sztipanovits, Gabor Karsai, Hubertus Franke
ICS
2000
Tsinghua U.
13 years 11 months ago
A simulation-based study of scheduling mechanisms for a dynamic cluster environment
Scheduling of processes onto processors of a parallel machine has always been an important and challenging area of research. The issue becomes even more crucial and di cult as we ...
Yanyong Zhang, Anand Sivasubramaniam, José ...
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
NIPS
2008
13 years 9 months ago
Natural Image Denoising with Convolutional Networks
We present an approach to low-level vision that combines two main ideas: the use of convolutional networks as an image processing architecture and an unsupervised learning procedu...
Viren Jain, H. Sebastian Seung