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JEC
2006
88views more  JEC 2006»
13 years 9 months ago
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
John Oliver, Ravishankar Rao, Diana Franklin, Fred...
ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
14 years 6 months ago
Limits on voltage scaling for caches utilizing fault tolerant techniques
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M...
SENSYS
2009
ACM
14 years 3 months ago
Integrated distributed energy awareness for wireless sensor networks
Energy in sensor networks is a distributed, non-transferable resource. Over time, differences in energy availability are likely to arise. Protocols like routing trees may concent...
Geoffrey Werner Challen, Jason Waterman, Matt Wels...
ADHOCNOW
2004
Springer
14 years 2 months ago
A Rate-Adaptive MAC Protocol for Low-Power Ultra-Wide Band Ad-Hoc Networks
Recent theoretical results show that it is optimal to allow interfering sources to transmit simultaneously as long as they are outside a well-defined exclusion region around a de...
Ruben Merz, Jean-Yves Le Boudec, Jörg Widmer,...
HPCA
2008
IEEE
14 years 9 months ago
A comprehensive approach to DRAM power management
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...
Ibrahim Hur, Calvin Lin