We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
John Oliver, Ravishankar Rao, Diana Franklin, Fred...
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M...
Energy in sensor networks is a distributed, non-transferable resource. Over time, differences in energy availability are likely to arise. Protocols like routing trees may concent...
Geoffrey Werner Challen, Jason Waterman, Matt Wels...
Recent theoretical results show that it is optimal to allow interfering sources to transmit simultaneously as long as they are outside a well-defined exclusion region around a de...
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...