54 search results - page 4 / 11 » Low power SRAM techniques for handheld products |
IOLTS
2008
IEEE
14 years 1 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
ECCTD
2011
12 years 7 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...