169 search results - page 4 / 34 » Low power architecture of the soft-output Viterbi algorithm |
ASAP
2009
IEEE
14 years 4 months ago
2009
IEEE
The advent of the mobile age has heavily changed the requirements of today’s communication devices. Data transmission over interference-prone wireless channels requires addition...
TVLSI
2010
13 years 2 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
PATMOS
2000
Springer
13 years 11 months ago
2000
Springer
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...