Sciweavers

143 search results - page 3 / 29
» Low power data processing by elimination of redundant comput...
Sort
View
ASAP
2009
IEEE
157views Hardware» more  ASAP 2009»
14 years 4 months ago
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
The advent of the mobile age has heavily changed the requirements of today’s communication devices. Data transmission over interference-prone wireless channels requires addition...
Andreas Genser, Christian Bachmann, Christian Steg...
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
14 years 1 months ago
A low complexity hardware architecture for motion estimation
This paper tackles the problem of accelerating The rest of this paper is organised as follows: section II motion estimation for video processing. A novel architecture details relat...
Daniel Larkin, Vlenti. Muresan, Noel E. O'Connor
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 19 days ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
ICCD
2008
IEEE
148views Hardware» more  ICCD 2008»
14 years 1 months ago
Adaptive SRAM memory for low power and high yield
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jaco...
AICCSA
2006
IEEE
168views Hardware» more  AICCSA 2006»
14 years 1 months ago
Power Efficient Algorithms for Computing Fast Fourier Transform over Wireless Sensor Networks
Collaborative signal processing is one of the most promising applications that are currently being investigated for sensor networks. In this paper, we use FFT computation as a veh...
Turkmen Canli, Ajay K. Gupta, Ashfaq A. Khokhar