331 search results - page 24 / 67 » Low power implementation of a turbo-decoder on programmable ... |
116
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
211
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
161
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CVIU
2010
15 years 6 months ago
2010
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
189
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DATE
1998
IEEE
15 years 10 months ago
1998
IEEE
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
171
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HPCA
2005
IEEE
15 years 11 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...