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IJCSA
2008
100views more  IJCSA 2008»
15 years 5 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel...
ASPLOS
2010
ACM
16 years 11 days ago
COMPASS: a programmable data prefetcher using idle GPU shaders
A traditional fixed-function graphics accelerator has evolved into a programmable general-purpose graphics processing unit over the last few years. These powerful computing cores...
Dong Hyuk Woo, Hsien-Hsin S. Lee
ERSA
2008
145views Hardware» more  ERSA 2008»
15 years 7 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
ERSA
2008
92views Hardware» more  ERSA 2008»
15 years 7 months ago
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning
This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
15 years 12 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh