82 search results - page 5 / 17 » Low power logic synthesis for XOR based circuits |
ISQED
2005
IEEE
14 years 29 days ago
2005
IEEE
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
ISVLSI
2002
IEEE
14 years 9 days ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
ASPDAC
2000
ACM
13 years 11 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
ISCAS
2005
IEEE
14 years 29 days ago
2005
IEEE
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...