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ISQED
2008
IEEE
120views Hardware» more  ISQED 2008»
14 years 2 months ago
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
Huifang Qin, Animesh Kumar, Kannan Ramchandran, Ja...
JCP
2008
216views more  JCP 2008»
13 years 8 months ago
Design Overview Of Processor Based Implantable Pacemaker
Implantable pacemaker is a battery operated real time embedded system, which includes software/hardware codesign strategy. As it is placed within the heart by surgery, battery life...
Santosh D. Chede, Kishore D. Kulat
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
14 years 2 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
14 years 2 months ago
Design methodology for global resonant H-tree clock distribution networks
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
Jonathan Rosenfeld, Eby G. Friedman
ISLPED
2007
ACM
104views Hardware» more  ISLPED 2007»
13 years 10 months ago
Low power soft-output signal detector design for wireless MIMO communication systems
Energy-efficient realization of soft-output signal detection is of great importance in emerging high-speed multiple-input multiple-output (MIMO) wireless communication systems. T...
Sizhong Chen, Tong Zhang