552 search results - page 23 / 111 » Low power techniques for Motion Estimation hardware |
DFT
2005
IEEE
14 years 15 hour ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
ICCAD
2004
IEEE
14 years 7 months ago
2004
IEEE
Wirelength estimation is an important tool to guide the design optimization process in early design stages. In this paper, we present a novel wirelength estimation technique calle...
ISQED
2007
IEEE
14 years 4 months ago
2007
IEEE
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...