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» Low power techniques for Motion Estimation hardware
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ICIP
2003
IEEE
16 years 7 months ago
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores
For motion estimation (ME) and discrete cosine transform (DCT) of MPEG video encoding, content variation and perceptual tolerance in video signals can be exploited to gracefully t...
Andrew Laffely, Jian Liang, Russell Tessier, Wayne...
ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
15 years 11 months ago
Low cost instruction cache designs for tag comparison elimination
Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comp...
Youtao Zhang, Jun Yang 0002
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
15 years 9 months ago
Transistor reordering rules for power reduction in CMOS gates
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
ICCAD
1994
IEEE
144views Hardware» more  ICCAD 1994»
15 years 10 months ago
Power analysis of embedded software: a first step towards software power minimization
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical com...
Vivek Tiwari, Sharad Malik, Andrew Wolfe
IPSN
2010
Springer
16 years 11 days ago
Distributed estimation of linear acceleration for improved accuracy in wireless inertial motion capture
Motion capture using wireless inertial measurement units (IMUs) has many advantages over other techniques. Achieving accurate tracking with IMUs presents a processing challenge, e...
A. D. Young, M. J. Ling, D. K. Arvind