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» Low power techniques for Motion Estimation hardware
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DATE
2000
IEEE
114views Hardware» more  DATE 2000»
15 years 10 months ago
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
Michael Münch, Norbert Wehn, Bernd Wurth, Ren...
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
15 years 3 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
ICCD
2008
IEEE
498views Hardware» more  ICCD 2008»
16 years 2 months ago
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
Hao Xu, Ranga Vemuri, Wen-Ben Jone
PPAM
2007
Springer
15 years 12 months ago
A Grid-Enabled Lattice-Boltzmann-Based Modelling System
Lattice-Boltzmann (LB) methods are a well-known technique in the context of computational fluid dynamics. By nature, they can easily be parallelized but their adaptation to the Gr...
Gérard Dethier, Cyril Briquet, Pierre March...
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
15 years 11 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John