552 search results - page 74 / 111 » Low power techniques for Motion Estimation hardware |
174
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ISQED
2007
IEEE
16 years 2 days ago
2007
IEEE
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
153
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ISCA
2007
IEEE
16 years 3 days ago
2007
IEEE
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
182
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DAC
2006
ACM
16 years 6 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
160
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DATE
2008
IEEE
16 years 8 days ago
2008
IEEE
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
168
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ISCA
2002
IEEE
15 years 10 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...