3 search results - page 1 / 1 » Low-Power High-Speed 180-nm CMOS Clock Drivers |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper reports a high speed and low power consumption direct–indirect bootstrapped full–swing CMOS inverter driver circuit (bfi–driver). The simulation results, based o...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...