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ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
14 years 29 days ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...
IEEEPACT
2005
IEEE
14 years 29 days ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
ICCAD
1994
IEEE
151views Hardware» more  ICCAD 1994»
13 years 11 months ago
Multi-way VLSI circuit partitioning based on dual net representation
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
Jason Cong, Wilburt Labio, Narayanan Shivakumar
DATE
2010
IEEE
193views Hardware» more  DATE 2010»
14 years 14 days ago
Coordinated resource optimization in behavioral synthesis
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
Jason Cong, Bin Liu, Junjuan Xu
CODES
2007
IEEE
14 years 1 months ago
Embedded software development on top of transaction-level models
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...
Wolfgang Klingauf, Robert Günzel, Christian S...