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DAC
2004
ACM
14 years 8 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
DAC
2005
ACM
14 years 8 months ago
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
ICRA
1995
IEEE
188views Robotics» more  ICRA 1995»
13 years 11 months ago
Fast Approximation of Range Images by Triangular Meshes Generated through Adaptive Randomized Sampling
This paper describes and evaluates an efficient technique that allows the fast generation of 3D triangular meshes from range images avoiding optimization procedures. Such a tool ...
Miguel Angel García
MOBIQUITOUS
2008
IEEE
14 years 2 months ago
ScreenSpot: multidimensional resource discovery for distributed applications in smart spaces
The big challenge related to the contemporary research on ubiquitous and pervasive computing is that of seamless integration. For the next generation of ubiquitous and distributed...
Marko Jurmu, Sebastian Boring, Jukka Riekki
DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy