36 search results - page 5 / 8 » MFAST: a single chip highly parallel image processing archit... |
IJPP
2006
13 years 7 months ago
2006
Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, co...
PPL
2008
13 years 7 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
ISCA
2010
IEEE
13 years 5 months ago
2010
IEEE
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
SBACPAD
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-dimensional imaging techniques involve the processing of high resolution images commonly used in medical, civil and remote-sensing applications. A barrier commonly encounter...