Sciweavers

23 search results - page 2 / 5
» MONGREL: Hybrid Techniques for Standard Cell Placement
Sort
View
ASPDAC
2011
ACM
297views Hardware» more  ASPDAC 2011»
12 years 11 months ago
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
Shashikanth Bobba, Ashutosh Chakraborty, Olivier T...
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 4 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
ISPD
2006
ACM
71views Hardware» more  ISPD 2006»
14 years 1 months ago
Satisfying whitespace requirements in top-down placement
In this invited note we outline several algorithms and features appearing in Capo 10, free open-source software for congestion-driven standard cell placement, mixed-size placement...
Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L....
ISPD
2000
ACM
145views Hardware» more  ISPD 2000»
13 years 11 months ago
A snap-on placement tool
The standard cell placement problem has been extensively studied in the past twenty years. Many approaches were proposed and proven e ective in practice. However, successful place...
Xiaojian Yang, Maogang Wang, Kenneth Eguro, Majid ...
ISPD
2010
ACM
224views Hardware» more  ISPD 2010»
14 years 2 months ago
An analytical placer for mixed-size 3D placement
Existing 3D placement techniques are mainly used for standardcell circuits, while mixed-size placement is needed to support highlevel functional units and intellectual property (I...
Jason Cong, Guojie Luo