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CODES
1996
IEEE
14 years 3 months ago
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
The partitioning of image processing algorithms with a novel hardware/software co-designframework (CoDe-X) is presented in this paper, where a new Xputer-architecture (parallel Ma...
Reiner W. Hartenstein, Jürgen Becker, Rainer ...
IJFCS
2007
63views more  IJFCS 2007»
13 years 11 months ago
Path-Equivalent Developments in Acyclic Weighted Automata
Weighted finite automata (WFA) are used with FPGA accelerating hardware to scan large genomic banks. Hardwiring such automata raises surface area and clock frequency constraints,...
Mathieu Giraud, Philippe Veber, Dominique Lavenier
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
14 years 5 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 9 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
HPCA
2011
IEEE
13 years 2 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...