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ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 2 months ago
Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters
We propose an analog current-mode subthreshold CMOS circuit implementing a neuromorphic oscillator. Our circuit is based on the half-center oscillator model proposed by Matsuoka, ...
Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
INTEGRATION
2010
172views more  INTEGRATION 2010»
13 years 7 months ago
Analog circuits optimization based on evolutionary computation techniques
1 — This paper presents a new design automation tool based on a modified genetic algorithm kernel, in order to increase efficiency on the analog circuit and system design cycle. ...
Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
IEICET
2007
75views more  IEICET 2007»
13 years 8 months ago
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits
We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation with noisy neural elements. Our aim is t...
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshi...
DAC
2004
ACM
14 years 9 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
DATE
2002
IEEE
151views Hardware» more  DATE 2002»
14 years 1 months ago
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets
In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These set...
Robert Schwencker, Frank Schenkel, Michael Pronath...