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NIPS
2003
13 years 8 months ago
A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors
A mixed-signal image filtering VLSI has been developed aiming at real-time generation of edge-based image vectors for robust image recognition. A four-stage asynchronous median de...
Masakazu Yagi, Hideo Yamasaki, Tadashi Shibata
IJCSA
2008
100views more  IJCSA 2008»
13 years 7 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel...
FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
14 years 18 days ago
Design of FPGA interconnect for multilevel metalization
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
Raphael Rubin, André DeHon
ICCAD
1999
IEEE
90views Hardware» more  ICCAD 1999»
13 years 11 months ago
An implicit connection graph maze routing algorithm for ECO routing
Abstract-- ECO routing is a very important design capability in advanced IC, MCM and PCB designs when additional routings need to be made at the latter stage of the physical design...
Jason Cong, Jie Fang, Kei-Yong Khoo
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
14 years 4 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel