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MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
14 years 4 months ago
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederi...
LCTRTS
2007
Springer
14 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
CASES
2006
ACM
14 years 3 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
ISCA
2010
IEEE
284views Hardware» more  ISCA 2010»
14 years 3 months ago
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address
Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and...
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
SIGMOD
2010
ACM
207views Database» more  SIGMOD 2010»
14 years 2 months ago
Automatic contention detection and amelioration for data-intensive operations
To take full advantage of the parallelism offered by a multicore machine, one must write parallel code. Writing parallel code is difficult. Even when one writes correct code, the...
John Cieslewicz, Kenneth A. Ross, Kyoho Satsumi, Y...