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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 8 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
15 years 8 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
16 years 23 days ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
OOPSLA
2007
Springer
15 years 10 months ago
Notation and representation in collaborative object-oriented design: an observational study
Software designers in the object-oriented paradigm can make use of modeling tools and standard notations such as UML. Nevertheless, casual observations from collocated design coll...
Uri Dekel, James D. Herbsleb
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 8 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...