Sciweavers

30 search results - page 4 / 6
» Mapping to Reduce Contention in Multiprocessor Architectures
Sort
View
CISIS
2010
IEEE
12 years 11 months ago
A Simple Improvement of the Work-stealing Scheduling Algorithm
Work-stealing is the todays algorithm of choice for dynamic load-balancing of irregular parallel applications on multiprocessor systems. We have evaluated the algorithm’s effic...
Zeljko Vrba, Pål Halvorsen, Carsten Griwodz
HPCA
2008
IEEE
14 years 7 months ago
Power-Efficient DRAM Speculation
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti,...
CODES
2004
IEEE
13 years 11 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
DAC
2008
ACM
14 years 8 months ago
ADAM: run-time agent-based distributed application mapping for on-chip communication
Design-time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. This drives the development of run-time adaptive s...
Jörg Henkel, Mohammad Abdullah Al Faruque, Ru...
ASPLOS
2008
ACM
13 years 9 months ago
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
Michal Wegiel, Chandra Krintz