66 search results - page 7 / 14 » Masking timing errors on speed-paths in logic circuits |
ETS
2011
IEEE
12 years 7 months ago
2011
IEEE
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-s...
PATMOS
2007
Springer
14 years 1 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
TCAD
2008
13 years 7 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
ITC
2003
IEEE
14 years 22 days ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...