391 search results - page 34 / 79 » Massively parallel processing on a chip |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
FPL
2003
Springer
14 years 25 days ago
2003
Springer
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
ISCA
2000
IEEE
14 years 1 hour ago
2000
IEEE
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially...
LCPC
2007
Springer
14 years 1 months ago
2007
Springer
Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private st...