325 search results - page 58 / 65 » Maximum margin planning |
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
Data center power infrastructure incurs massive capital costs, which typically exceed energy costs over the life of the facility. To squeeze maximum value from the infrastructure,...
ICDAR
2007
IEEE
14 years 1 months ago
2007
IEEE
The Machine Learning and Pattern Recognition communities are facing two challenges: solving the normalization problem, and solving the deep learning problem. The normalization pro...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
MICRO
2003
IEEE
14 years 27 days ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
GLVLSI
2010
IEEE
14 years 22 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...