133 search results - page 4 / 27 » Measuring the Performance of Multimedia Instruction Sets |
IEEEPACT
2002
IEEE
14 years 27 days ago
2002
IEEE
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
CSE
2008
IEEE
13 years 9 months ago
2008
IEEE
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. A...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
VEE
2006
ACM
14 years 1 months ago
2006
ACM
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speci...
CODES
1998
IEEE
14 years 7 days ago
1998
IEEE
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...