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IPPS
1995
IEEE
13 years 11 months ago
The RACE network architecture
The RACE R parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE ...
Bradley C. Kuszmaul
CODES
2003
IEEE
14 years 28 days ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
ICCAD
2007
IEEE
119views Hardware» more  ICCAD 2007»
13 years 9 months ago
IntSim: A CAD tool for optimization of multilevel interconnect networks
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffre...
CASES
2007
ACM
13 years 11 months ago
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of...
Chengmo Yang, Alex Orailoglu
GLOBECOM
2008
IEEE
14 years 2 months ago
Towards Secure Link Quality Measurement in Multihop Wireless Networks
Abstract— Link quality measurement (LQM), i.e. packet reception ratio (PRR) measurement, is becoming an indispensable component in multihop wireless networks. However, in all the...
Kai Zeng, Shucheng Yu, Kui Ren, Wenjing Lou, Yanch...