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ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
15 years 2 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
ECSA
2011
Springer
14 years 4 months ago
Delta-oriented architectural variability using MontiCore
Modeling of software architectures is a fundamental part of software development processes. Reuse of software components and early analysis of software topologies allow the reduct...
Arne Haber, Thomas Kutz, Holger Rendel, Bernhard R...
SOSP
2009
ACM
16 years 1 months ago
Automatically patching errors in deployed software
We present ClearView, a system for automatically patching errors in deployed software. ClearView works on stripped Windows x86 binaries without any need for source code, debugging...
Jeff H. Perkins, Sunghun Kim, Samuel Larsen, Saman...
ICS
2009
Tsinghua U.
15 years 11 months ago
Less reused filter: improving l2 cache performance via filtering less reused lines
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
Lingxiang Xiang, Tianzhou Chen, Qingsong Shi, Wei ...
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BMCBI
2010
119views more  BMCBI 2010»
15 years 4 months ago
Multi-task learning for cross-platform siRNA efficacy prediction: an in-silico study
Background: Gene silencing using exogenous small interfering RNAs (siRNAs) is now a widespread molecular tool for gene functional study and new-drug target identification. The key...
Qi Liu, Qian Xu, Vincent Wenchen Zheng, Hong Xue, ...