98 search results - page 14 / 20 » Memory Access Scheduling Schemes for Systems with Multi-Core... |
126
Voted
ISCA
1994
IEEE
15 years 7 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
141
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DATE
2010
IEEE
15 years 8 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
155
Voted
ASPLOS
2010
ACM
15 years 6 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
128
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ASPDAC
2006
ACM
15 years 9 months ago
2006
ACM
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
136
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EUROPAR
2008
Springer
15 years 5 months ago
2008
Springer
Over the last decade, Message Passing Interface (MPI) has become a very successful parallel programming environment for distributed memory architectures such as clusters. However, ...