95 search results - page 1 / 19 » Memory Aware High-Level Synthesis for Embedded Systems |
CORR
2006
Springer
13 years 7 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
FDL
2007
IEEE
14 years 1 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...