236 search results - page 33 / 48 » Memory Bank Predictors |
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
VCIP
2003
13 years 9 months ago
2003
A new set of boundary-handling algorithms has been developed for discrete wavelet transforms in the ISO/IEC JPEG-2000 Still Image Coding Standard. Two polyphase component extrapol...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...