Sciweavers

745 search results - page 107 / 149
» Memory Exploration for Low Power, Embedded Systems
Sort
View
IESS
2007
Springer
116views Hardware» more  IESS 2007»
14 years 4 months ago
Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes
This work investigates the use of reconfigurable devices as computing platform for self-organizing embedded systems. Those usually consist of a set of distributed, autonomous node...
Dominik Murr, Felix Mühlbauer, Falko Dressler...
CAL
2008
13 years 10 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
CASES
2005
ACM
14 years 7 days ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
ARCS
2004
Springer
14 years 2 months ago
Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing
: This paper reports ongoing work towards a dynamically reconfigurable System-on-Chip (SoC) platform for video signal processing. It consists of dedicated, statically and dynamical...
Walter Stechele, Stephan Herrmann, Andreas Herkers...
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 3 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati