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» Memory Exploration for Low Power, Embedded Systems
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PATMOS
2000
Springer
13 years 11 months ago
Dynamic Memory Design for Low Data-Retention Power
Abstract. The emergence of data-intensive applications in mobile environments has resulted in portable electronic systems with increasingly large dynamic memories. The typical oper...
Joohee Kim, Marios C. Papaefthymiou
HOTI
2008
IEEE
14 years 2 months ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
EIT
2009
IEEE
14 years 2 months ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
Zhongbo Cao, Ramon Mercado, Diane T. Rover
DAC
2008
ACM
14 years 8 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu