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» Memory Exploration for Low Power, Embedded Systems
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PATMOS
2004
Springer
14 years 1 months ago
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems
Portableembeddeddevicesmustpresentlyrunmultimediaandwireless network applications with enormous computational performance requirements at a low energy consumption. In these applica...
David Atienza, Stylianos Mamagkakis, Francky Catth...
ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda
DCC
2000
IEEE
14 years 3 days ago
Arithmetic Coding for Low Power Embedded System Design
We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumpti...
Haris Lekatsas, Wayne Wolf, Jörg Henkel
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
14 years 19 days ago
Memory System Connectivity Exploration
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau