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» Memory Exploration for Low Power, Embedded Systems
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VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 10 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
FAST
2011
13 years 1 months ago
CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives
Although Flash Memory based Solid State Drive (SSD) exhibits high performance and low power consumption, a critical concern is its limited lifespan along with the associated relia...
Feng Chen, Tian Luo, Xiaodong Zhang
SAMOS
2007
Springer
14 years 4 months ago
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
Nainesh Agarwal, Nikitas J. Dimopoulos
CODES
2004
IEEE
14 years 1 months ago
Dynamic overlay of scratchpad memory for energy minimization
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
Manish Verma, Lars Wehmeyer, Peter Marwedel
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
14 years 3 months ago
Constrained Power Management: Application to a multimedia mobile platform
—In this paper we provide an overview of CPM, a cross-layer framework for Constrained Power Management, and we present its application on a real use case. This framework involves...
Patrick Bellasi, Stefano Bosisio, Matteo Carnevali...