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JVCIR
2008
92views more  JVCIR 2008»
13 years 9 months ago
Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications
This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The soft...
Dionisis Chaikalis, Nikos Sgouros, Dimitris Maroul...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
14 years 2 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
FPL
2007
Springer
105views Hardware» more  FPL 2007»
14 years 3 months ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl
TC
2008
13 years 9 months ago
Secure Memory Accesses on Networks-on-Chip
Security is gaining relevance in the development of embedded devices. Toward a secure system at each level of design, this paper addresses security aspects related to Network-on-Ch...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood