110 search results - page 5 / 22 » Memory hierarchy exploration for low power architectures in ... |
FPL
2005
Springer
14 years 6 days ago
2005
Springer
Domain-specific heterogeneous reconfigurable arrays provide high performance over generic Field Programmable Gate Arrays (FPGAs) while maintaining the flexibility for that particu...
ISLPED
2003
ACM
13 years 12 months ago
2003
ACM
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set ...
EH
2004
IEEE
13 years 10 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
ISSS
2002
IEEE
13 years 11 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
ISLPED
2005
ACM
14 years 7 days ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...