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GI
2009
Springer
14 years 1 months ago
Tapir: Language Support to Reduce the State Space in Model-Checking
: Model-checking is a way of testing the correctness of concurrent programs. To do so, a model of the program is proven to match properties and constraints specified by the progra...
Ronald Veldema, Michael Philippsen
EVOW
2001
Springer
14 years 1 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
FATES
2006
Springer
14 years 13 days ago
A Symbolic Framework for Model-Based Testing
Abstract. The starting point for Model-Based Testing is an implementation relation that formally defines when a formal model representing the System Under Test conforms to a formal...
Lars Frantzen, Jan Tretmans, Tim A. C. Willemse
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
14 years 9 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...
SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
14 years 2 months ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar