14 search results - page 2 / 3 » Methodologies and Algorithms for Testing Switch-Based NoC In... |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...
VTS
2002
IEEE
14 years 17 days ago
2002
IEEE
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
ITC
2003
IEEE
14 years 29 days ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...