27 search results - page 4 / 6 » Methodologies for Tolerating Cell and Interconnect Faults in... |
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a methodology for the simulation of soft errors targeting future nano-technological devices. This approach efficiently scales the failure rate of individual devices ac...
COMPSAC
2007
IEEE
13 years 11 months ago
2007
IEEE
The world is increasingly dependent on critical infrastructures such as the electric power grid, water, gas, and oil transport systems, which are susceptible to cascading failures...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
CF
2004
ACM
14 years 1 months ago
2004
ACM
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...