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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 4 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 4 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
ICCAD
2001
IEEE
217views Hardware» more  ICCAD 2001»
14 years 7 months ago
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
Michael Krasnicki, Rodney Phelps, James R. Hellums...
NOCS
2009
IEEE
14 years 5 months ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
ISCAS
2008
IEEE
141views Hardware» more  ISCAS 2008»
14 years 5 months ago
AMBA AHB bus potocol checker with efficient debugging mechanism
—Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-tomarket, thus how to verify IP functionality on bus protocol is a...
Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang