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DAC
2007
ACM
14 years 8 months ago
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 21 days ago
Extending JTAG for Testing Signal Integrity in SoCs
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically,...
Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nour...
DAC
2001
ACM
14 years 8 months ago
SoC Integration of Reusable Baseband Bluetooth IP
This presentation will give a list of design criteria an ASIC Design house need to look in the process of deciding to take the complex Bluetooth specification and implement everyt...
Barry Clark, Torbjörn Grahm
ISCAS
2007
IEEE
111views Hardware» more  ISCAS 2007»
14 years 1 months ago
Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform
—Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, we propose a heterogeneous p...
Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdoga...
ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
14 years 21 days ago
SoC design integration by using automatic interconnection rectification
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou