96 search results - page 16 / 20 » Microarchitectural techniques for power gating of execution ... |
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
MICRO
1996
IEEE
13 years 11 months ago
1996
IEEE
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
CGO
2005
IEEE
14 years 1 months ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...