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ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
14 years 23 days ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
PPOPP
2006
ACM
14 years 1 months ago
A case study in top-down performance estimation for a large-scale parallel application
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
Ilya Sharapov, Robert Kroeger, Guy Delamarter, Raz...
HPCA
2003
IEEE
14 years 7 months ago
A Statistically Rigorous Approach for Improving Simulation Methodology
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
14 years 22 days ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
ASPLOS
2010
ACM
14 years 2 months ago
Characterizing processor thermal behavior
Temperature is a dominant factor in the performance, reliability, and leakage power consumption of modern processors. As a result, increasing numbers of researchers evaluate therm...
Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jo...