This paper presents a novel source code transformation for control flow optimizationcalled loop nest splitting which minimizes the number of executed if-statements in loop nests ...
The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with tech...
Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckle...
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...