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ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
13 years 5 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
ITCC
2005
IEEE
14 years 29 days ago
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks
This paper presents a high performance and scalable elliptic curve processor which is designed to be resistant against timing attacks. The point multiplication algorithm (double-a...
Alireza Hodjat, David Hwang, Ingrid Verbauwhede
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 4 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
IEEESCC
2009
IEEE
13 years 5 months ago
Theoretical Framework for Eliminating Redundancy in Workflows
In this paper we look at combining and compressing a set of workflows, such that computation can be minimized. In this context, we look at two novel theoretical problems with appl...
Dhrubajyoti Saha, Abhishek Samanta, Smruti R. Sara...
TCAD
2010
194views more  TCAD 2010»
13 years 2 months ago
Layout Decomposition Approaches for Double Patterning Lithography
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...