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APLAS
2007
ACM
13 years 11 months ago
Local Reasoning for Storable Locks and Threads
We present a resource oriented program logic that is able to reason about concurrent heap-manipulating programs with unbounded numbers of dynamically-allocated locks and threads. T...
Alexey Gotsman, Josh Berdine, Byron Cook, Noam Rin...
IOLTS
2008
IEEE
83views Hardware» more  IOLTS 2008»
14 years 2 months ago
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, ...
WEA
2010
Springer
397views Algorithms» more  WEA 2010»
14 years 2 months ago
A New Combinational Logic Minimization Technique with Applications to Cryptology
Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured ...
Joan Boyar, René Peralta
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
CSREAESA
2004
13 years 9 months ago
Switching Activity Minimization in Combinational Logic Design
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...